Centaur Technology

» see centtech.com as it lived, on the wayback machine

~ the goodbye ~

Centaur Technology was founded in Austin in April 1995 by Glenn Henry and Terry Parks, with two other co-founders. Henry had done twenty-one years at IBM, where he was named an IBM Fellow in 1985 and led the architecture on the System/38 that became the AS/400. He left in 1988 for Dell, as its first head of research and development and later its chief technology officer. He wanted to go back to designing processors with a small group, and Len Perham at Integrated Device Technology agreed to fund exactly that.

The pitch was that Intel's cores were optimized for things most users never touched. Centaur would draw a much smaller die by leaving out the expensive parts, and sell into the segment that cared about price and power rather than about the top of a benchmark chart. Three designs shipped under IDT's marketing name, WinChip, with the first introduced at the Fall Microprocessor Forum in 1997.

VIA Technologies bought Centaur from IDT in September 1999, and that purchase is what kept it alive for another twenty-two years. The VIA C3 came out of Austin in five variants, with the C7 behind it. Then came the Nano, which was Centaur's first out-of-order design and its first 64-bit one. These were the chips in fanless boxes and in the small cheap laptops that briefly had a market in the late 2000s.

Along the way Centaur did something the larger companies had not. Starting with a C7 part in 2004, VIA shipped hardware acceleration for encryption and for random number generation under the name PadLock. Intel and AMD got to AES instructions in 2008 and Intel added RDRAND in 2015, which puts a small team in Texas somewhere between four and eleven years ahead on a feature that is now in everything.

~ the chronicle ~

~ the small team ~

The design philosophy is the interesting artifact here, because it was deliberately unfashionable. Clock frequency was favored over doing more per clock, and rarely used x86 instructions were emulated in microcode rather than built in hardware. Out-of-order execution was left out on purpose for years, on the grounds that it eats die area and holds down the clock while doing very little for the workloads these chips actually ran.

What Centaur did spend transistors on was memory. The primary caches were generous, with 128KB standing as a Centaur signature for years. The prefetch and branch prediction work was where the rest of the effort went. The reasoning was that a simple core fed well beats a complicated core fed badly on most real code, and for two decades of low-power x86 parts that turned out to be defensible. The die comparisons are the clearest statement of it. Four C7 cores fit in roughly the area of one Pentium 4 Prescott core on the same process.

~ the last chip ~

In late 2019 Centaur announced CNS, an x86-64 core with AVX-512, and the CHA system on chip built around eight of them with a 4096-wide deep learning coprocessor called Ncore sitting on the same die. It ran at 2 GHz base on TSMC's 16nm process and used an LGA2011 socket that looked like Intel's and was not electrically compatible with it. The part was submitted to MLPerf Inference v0.5, where among all the closed-division entrants its MobileNetv1 stream result had the lowest latency of anything benchmarked. That is a real result from a company most people in the industry could not place, and it was the last thing Centaur ever announced.

~ the price of a design team ~

VIA filed the deal with the Taiwan Stock Exchange on 4 November 2021. Intel would recruit the majority of Centaur's employees and pay VIA $125 million for the privilege, with covenants attached. VIA kept the x86 license and the patents, including the finished CHA design, and had nobody left who could support any of it. The CNS chip was canceled. Zhaoxin, the joint venture that had been refining the Nano design in China, carried on.

Twenty-six years of processor architecture and the buyer wanted none of it. This is the part I keep looking at, because it happened in the field I work in now. I spend my days on edge inference, models running on constrained hardware in places with no room for a server, and the final Centaur chip was an x86 part with a deep learning accelerator welded onto it for exactly that problem. A grave on this site is usually something from a decade I can see from a distance. This one closed while I was already working on the thing it was built for, and I still had to go and read about it afterwards.

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